The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in the present disclosure and are not admitted to be prior art by inclusion in this section.
Conventional retention flip-flops use additional keeper transistors and isolated N-wells for power-gated and always-on components. This can result in an area approximately 3.5 times as large and a 30% increase in delay compared to a non-retention flip-flop.